High-voltage metal-oxide-semiconductor device

ABSTRACT

A high-voltage MOS transistor includes a gate overlying an active area of a semiconductor substrate; a drain doping region pulled back away from an edge of the gate by a distance L; a first lightly doped region between the gate and the drain doping region; a source doping region in a first ion well; and a second lightly doped region between the gate and the source doping region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a high-voltage device structure. Moreparticularly, the present invention relates to a high-voltagemetal-oxide-semiconductor (HVMOS) device structure.

2. Description of the Prior Art

High-voltage metal-oxide-semiconductors are MOS devices for use underhigh voltages, which may be, but not limited to, voltages higher thanthe voltage supplied to the I/O circuit. HVMOS devices may function asswitches and are broadly utilized in audio output drivers, CPU powersupplies, power management systems, AC/DC converters, LCD or plasmatelevision drivers, automobile electronic components, PC peripheraldevices, small DC motor controllers, and other consumer electronicdevices.

FIG. 1 is a schematic, cross-sectional view of a conventionalhigh-voltage NMOS device. As shown in FIG. 1, the high-voltage NMOSdevice 101 includes a gate 210 overlying an area of a P type substrate100, a deep N well (DNW) 110 formed in the substrate 100, an N well 120formed in the substrate 100 proximate a first edge 210 a of the gate 210and doped with a first concentration of an N type dopant, a channelregion 130 doped with a first concentration of a P type dopantunderlying a portion of the gate 210 adjacent the N well 120, a shallowtrench isolation (STI) region 160 formed in the first portion of the Nwell 120, and an N+ tap region 150 to the second portion of the N well120 distal from the first edge 210 a of the gate 210. An N type sourceregion 155 including an N+ region and an N type lightly doped region 155b is formed in the P well 140 proximate a second edge 210 b of the gate210 opposite to the first edge 210 a.

The N+ tap region 150 is formed between the STI region 160 and the STIregion 162. The N+ tap region 150 is not self-aligned with the gate 210but is separated from the gate 210 by a distance D. The above-describedhigh-voltage NMOS device 101 utilizes STI region 160 to drop drainvoltage and makes high drain sustained voltage. Besides, theabove-described high-voltage NMOS device 101 can use well implant toform drain terminal.

However, the above-described high-voltage NMOS device 101 cannot beoperated when the drain is negatively biased because the junctionbetween the DNW 110 and the P type substrate 100 will be turned on andthus causes leakage. In some circumstances, it is desirable to have ahigh-voltage NMOS device and the drain terminal thereof can benegatively biased.

SUMMARY OF THE INVENTION

It is one objective of this invention to provide an improved HVMOSdevice structure that is COMS compatible and is operable when the drainterminal is negatively biased.

It is another objective of this invention to provide an improved HVMOSdevice structure with improved time dependent dielectric breakdown(TDDB) characteristic and reduced hot carrier injection (HCI) effect.

To these ends, according to one aspect of the present invention, thereis provided a high-voltage MOS transistor comprising a gate overlying anactive area of a semiconductor substrate; a drain doping region of afirst conductivity type pulled back away from an edge of the gate by adistance L; a first lightly doped region of the first conductivity typebetween the gate and the drain doping region; a source doping region ofthe first conductivity type in a first ion well of a second conductivitytype; and a second lightly doped region of the first conductivity typebetween the gate and the source doping region.

From one aspect of this invention, a high-voltage MOS transistorcomprises a gate overlying an active area of a semiconductor substrate;a drain structure of a first conductivity type at one side of the gate,wherein the drain structure comprises a first heavily doping regionspaced apart from a second heavily doping region that is proximate tothe gate, a first lightly doped region interposed between the first andsecond heavily doping regions, and a second lightly doped region betweenthe gate and the second heavily doping region; a source doping region ofthe first conductivity type in a first ion well of a second conductivitytype at the other side of the gate; and a third lightly doped region ofthe first conductivity type between the gate and the source dopingregion.

These and other objectives of the present invention will no doubt becomeobvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment that isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic, cross-sectional diagram illustrating aconventional high-voltage NMOS device.

FIG. 2 is an exemplary layout of the improved HVMOS structure inaccordance with one embodiment of this invention.

FIG. 3 is a schematic, cross-sectional view taken alone line I-I′ ofFIG. 2.

FIG. 4 is a schematic, cross-sectional diagram showing a high-voltageNMOS transistor structure in accordance with another embodiment of thisinvention.

FIG. 5 is a schematic, cross-sectional diagram showing a symmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention.

FIG. 6 is a schematic, cross-sectional diagram showing a high-voltageNMOS transistor structure in accordance with yet another embodiment ofthis invention.

FIG. 7 is a schematic, cross-sectional diagram showing a symmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention.

FIG. 8 is a schematic, cross-sectional diagram showing an asymmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention.

DETAILED DESCRIPTION

The present invention has been particularly shown and described withrespect to certain embodiments and specific features thereof. Theembodiments set forth hereinbelow are to be taken as illustrative ratherthan limiting. It should be readily apparent to those of ordinary skillin the art that various changes and modifications in form and detail maybe made without departing from the spirit and scope of the invention.

The exemplary structures of HVMOS transistor according to the presentinvention are described in detail. The improved HVMOS transistorstructure is described for a high-voltage NMOS transistor, but it shouldbe understood by those skilled in the art that by reversing the polarityof the conductive dopants high-voltage PMOS transistors can be made.

FIG. 2 is an exemplary layout of the improved high-voltage NMOStransistor structure in accordance with one embodiment of thisinvention. FIG. 3 is a schematic, cross-sectional view taken alone lineI-I′ of FIG. 2. As shown in FIGS. 2 and 3, the high-voltage NMOStransistor 1 is formed in an active area or oxide defined (OD) area 18that is surrounded by a shallow trench isolation (STI) region 16. Thehigh-voltage NMOS transistor 1 comprises a gate 21 overlying the activearea 18. The gate 21 may comprise polysilicon, metal, silicide or acombination thereof. The high-voltage NMOS transistor 1 furthercomprises a deep N well (DNW) 11 formed in the P type silicon substrate10 for bulk isolation. It is worth noted that the DNW 11 may be omittedin some PMOS cases.

On one side of the gate 21, an N+ drain doping region 12 is implantedinto the active area 18 of the P type silicon substrate 10 that has afirst concentration of P type dopants. It is one germane feature of thisinvention that the N+ drain doping region 12 is not aligned with theedge of the gate 21 and is pulled back away from the edge of the gate bya distance L. By doing this, the voltage drop of drain side is increasedand the time dependent dielectric breakdown (TDDB) of the gatedielectric layer 24 between the gate 21 and the drain is improved. An Ntype lightly doped region 14 is disposed between the edge of the gate 21and the N+ drain doping region 12. The N type lightly doped region 14extends laterally underneath a sidewall spacer 22 a that is formed on asidewall of the gate 21.

On the other side of the gate 21, an N+ source doping region 13 isimplanted into a P well 20 within the active area 18. The P well 20 hasa second concentration of P type dopants that is higher than the firstconcentration. The N+ source doping region 13 is substantially alignedwith the edge of the gate 21. An N type lightly doped region 15 isprovided underneath the sidewall spacer 22 b opposite to the sidewallspacer 22 a. Since the N+ drain doping region 12 is formed in the P typesilicon substrate 10 instead of formed in a P well, the hot carrierinjection (HCI) effect can be reduced.

A channel region 30 is defined between the N type lightly doped region14 and the N type lightly doped region 15 under the gate 21. As bestseen in FIG. 3, the channel region 30 may comprise a first portion 30 aof the P well 20 and a second portion 30 b of the P type siliconsubstrate 10. Accordingly, the high-voltage NMOS transistor 1 hasdifferent P type doping concentrations across the channel region 30. Agate dielectric layer 24 such as silicon dioxide is formed between thegate 21 and the channel region 30.

It is another feature of the present invention that the gate 21 maycomprise two portions: the first portion 21 a and the second portion 21b. The first portion 21 a of the gate 21 has a first concentration of Ntype dopants. The second portion 21 b, which is proximate to the N+drain doping region 12, has a second concentration of N type dopants.According to this invention, the second concentration may be lower thanthe first concentration.

For example, the second portion 21 b and the extended N type lightlydoped region 14 may be formed concurrently by masking the gate 21, thesidewall spacer 22 a and a portion of the active area 18 during the N+source/drain ion implantation process with a source/drain block layer32. It should be noted that the boundary between portions 21 a and 21 bmay be aligned with the boundary between the P well 20 and the substrate10 or not. Since the second portion 21 b has a reduced gate dopantconcentration, the TDDB characteristic of the gate dielectric layer 24between the gate 21 and the drain is significantly improved.

As best seen in FIG. 3, the high-voltage NMOS transistor 1 can beoperated under the following conditions, for example, including: a gatevoltage of −2V˜0V, a source voltage of −4V, a drain voltage of −4V and asubstrate voltage of −4V. It is one germane feature of this inventionthat the drain terminal can be negatively biased.

FIG. 4 is a schematic, cross-sectional diagram showing a high-voltageNMOS transistor structure in accordance with another embodiment of thisinvention, wherein like numeral numbers designate like regions, layersor elements. As shown in FIG. 4, the high-voltage NMOS transistor 1 acomprises a gate 21 overlying an active area surrounded by an STI region16, an N+drain doping region 12 and an N+ source doping region 13 in theP well 20, and deep N well 11 in the P type silicon substrate 10 forbulk isolation.

Likewise, the N+ drain doping region 12 is pulled back away from theedge of the gate 21 by a distance L for increasing the drain sidevoltage drop and improving TDDB. An N type lightly doped region 14 isdisposed between the edge of the gate 21 and the N+ drain doping region12. The N type lightly doped region 14 extends laterally underneath asidewall spacer 22 a that is formed on a sidewall of the gate 21. An Ntype lightly doped region 15 is provided underneath the sidewall spacer22 b opposite to the sidewall spacer 22 a. The gate 21 may comprise twoportions: the first portion 21 a and the second portion 21 b. The firstportion 21 a of the gate 21 has a first concentration of N type dopants.The second portion 21 b, which is proximate to the N+ drain dopingregion 12, has a second concentration of N type dopants. According tothis invention, the second concentration is lower than the firstconcentration.

FIG. 5 is a schematic, cross-sectional diagram showing a symmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention, wherein like numeral numbers designatelike regions, layers or elements. As shown in FIG. 5, the high-voltageNMOS transistor 1 b comprises a gate 21 overlying an active areasurrounded by an STI region 16, an N+ drain doping region 12 and an N+source doping region 42 both in a P well 20, and deep N well 11 in the Ptype silicon substrate 10 for bulk isolation. The N+ drain doping region12 and the N+ source doping region 42 are both pulled back away from theedge of the gate 21 by distance L₁ and distance L₂ respectively. In oneembodiment, the distance L₁ is equal to distance L₂.

An N type lightly doped region 14 is disposed between the edge of thegate 21 and the N+ drain doping region 12. The N type lightly dopedregion 14 extends laterally underneath a sidewall spacer 22 a. An N typelightly doped region 44 is disposed between the other edge of the gate21 and the N+ source doping region 42. The N type lightly doped region44 extends laterally underneath a sidewall spacer 22 b opposite to thesidewall spacer 22 a.

The gate 21 may comprise three portions: the first portion 21 a, thesecond portion 21 b and the third portion 21 c. The first portion 21 ais sandwiched between the second and third portions 21 b and 21 c. Thefirst portion 21 a of the gate 21 has a first concentration of N typedopants. The second portion 21 b, which is proximate to the N+ draindoping region 12, has a second concentration of N type dopants. Thethird portion 21 c, which is proximate to the N+ source doping region42, has a third concentration of N type dopants. According to thisinvention, the first concentration is higher than the second or thirdconcentration. In one embodiment, the second concentration issubstantially equal to the third concentration.

FIG. 6 is a schematic, cross-sectional diagram showing a high-voltageNMOS transistor structure in accordance with yet another embodiment ofthis invention, wherein like numeral numbers designate like regions,layers or elements. As shown in FIG. 6, the high-voltage NMOS transistor1 c comprises a gate 21 overlying an active area surrounded by an STIregion 16, an N+ source doping region 13 proximate to the spacer 22 b ina P well 20, an N type lightly doped region 15 underneath the spacer 22b, and deep N well 11 in the P type silicon substrate 10 for bulkisolation.

The high-voltage NMOS transistor 1 c further comprises a drain structure50 in the P well 20. The drain structure 50 is proximate to the spacer22 a and comprises a first N+ doping region 52 spaced apart from asecond N+ doping region 54 that is proximate to the gate 21. The drainstructure 50 further comprises a first N type lightly doped region 62interposed between the first and second N+ doping regions 52 and 54, anda second N type lightly doped region 64 disposed underneath the spacer22 a. To form the drain structure 50 and the N+ source doping region 13,for example, a source/drain block layer may be disposed above the firstN type lightly doped region 62 during the N+ source/drain ionimplantation process that is otherwise self-aligned with the gate 21 andthe spacers 22 a and 22 b. The unique drain structure 50 has increasedseries resistance and the TDDB characteristic can be improved.

FIG. 7 is a schematic, cross-sectional diagram showing a symmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention, wherein like numeral numbers designatelike regions, layers or elements. As shown in FIG. 7, the high-voltageNMOS transistor 1 d comprises a gate 21 overlying an active areasurrounded by an STI region 16, a drain structure 50 and a sourcestructure 70 in a P well 20, and deep N well 11 in the P type siliconsubstrate 10 for bulk isolation. The drain structure 50 of thehigh-voltage NMOS transistor 1 d may be identical to that as set forthin FIG. 6.

Likewise, the drain structure 50 is proximate to the spacer 22 a andcomprises a first N+ doping region 52 spaced apart from a second N+doping region 54 that is proximate to the gate 21. The drain structure50 further comprises a first N type lightly doped region 62 interposedbetween the first and second N+ doping regions 52 and 54, and a second Ntype lightly doped region 64 disposed underneath the spacer 22 a. Thesource structure 70 may be a mirror image of the drain structure 50. Thesource structure 70 is proximate to the spacer 22 b and comprises afirst N+ doping region 72 spaced apart from a second N+ doping region 74that is proximate to the gate 21. The drain structure 70 furthercomprises a first N type lightly doped region 82 interposed between thefirst and second N+ doping regions 72 and 74, and a second N typelightly doped region 84 disposed underneath the spacer 22 b.

FIG. 8 is a schematic, cross-sectional diagram showing a asymmetrichigh-voltage NMOS transistor structure in accordance with yet anotherembodiment of this invention, wherein like numeral numbers designatelike regions, layers or elements. As shown in FIG. 8, the high-voltageNMOS transistor 1 e comprises a gate 21 overlying an active areasurrounded by an STI region 16, a drain structure 50 in the P typesilicon substrate 10, and deep N well 11 in the P type silicon substrate10 for bulk isolation. The drain structure 50 of the high-voltage NMOStransistor 1 e may be substantially identical to that as set forth inFIG. 6 except for that the drain structure 50 is not formed in the Pwell 20. On the other side of the gate 21 (opposite to the drainstructure 50), an N+ source doping region 42 is provided in the P well20. The N+ source doping region 42 is pulled back away from the edge ofthe gate 21 by distance L₂. An N type lightly doped region 44 isdisposed between the edge of the gate 21 and the N+ source doping region42. The N type lightly doped region 44 extends laterally underneath asidewall spacer 22 b opposite to the sidewall spacer 22 a.

The gate 21 may comprise two portions: the first portion 21 a and thesecond portion 21 b. The first portion 21 a of the gate 21 has a firstconcentration of N type dopants. The second portion 21 b, which isproximate to the N+ source doping region 42, has a second concentrationof N type dopants. According to this invention, the first concentrationmay be higher than the second concentration. The channel region 30 maycomprise a first portion 30 a of the P well 20 and a second portion 30 bof the P type silicon substrate 10. Accordingly, the high-voltage NMOStransistor 1 e has different P type doping concentrations across thechannel region 30.

To sum up, the present invention high-voltage MOS transistor at leastincludes the following features.

(i) The present invention high-voltage MOS transistor is compatible withstandard CMOS processes and no additional cost is required.

(ii) The deep N well (DNW) may be introduced for bulk isolation.

(iii) In some embodiments, the drain structure is formed in the native Ptype silicon substrate, while the source terminal is formed in the Pwell. By doing this, the hot carrier injection (HCI) effect is reduced.

(iv) The gate doping concentration may be reduced at gate/drainoverlapping region to increase TDDB of gate oxide in the gate/drainoverlapping region.

(v) The N+ drain doping regions that is pulled back away from the edgeof the gate increase the voltage drop of drain side and improve TDDB.

(vi) The introduction of the source/drain block layer during the N+source/drain ion implantation process creates a unique drain structure50 having increased series resistance and improved TDDB characteristic.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. A high-voltage MOS transistor, comprising: a gate overlying an activearea of a semiconductor substrate; a drain doping region of a firstconductivity type pulled back away from an edge of the gate by adistance L; a first lightly doped region of the first conductivity typebetween the gate and the drain doping region; a source doping region ofthe first conductivity type in a first ion well of a second conductivitytype; and a second lightly doped region of the first conductivity typebetween the gate and the source doping region.
 2. The high voltage MOStransistor according to claim 1, wherein the semiconductor substrate isof the second conductivity type, the high voltage MOS transistor furthercomprises a second ion well of the first conductivity type in thesemiconductor substrate for bulk isolation, wherein the first ion wellis above the second ion well.
 3. The high voltage MOS transistoraccording to claim 1 wherein a channel region is defined between thefirst and second lightly doped regions under the gate.
 4. The highvoltage MOS transistor according to claim 3 wherein the channel regioncomprises a first portion of the first ion well and a second portion ofthe semiconductor substrate.
 5. The high voltage MOS transistoraccording to claim 3 further comprising a gate dielectric layer betweenthe gate and the channel region.
 6. The high voltage MOS transistoraccording to claim 1 wherein the gate comprises two portions: a firstportion and a second portion, and wherein the first portion of the gatehas a first concentration of dopants, the second portion, which isproximate to the drain doping region, has a second concentration ofdopants.
 7. The high voltage MOS transistor according to claim 6 whereinthe second concentration is lower than the first concentration.
 8. Thehigh voltage MOS transistor according to claim 2 wherein the draindoping region is formed in the semiconductor substrate above the secondion well.
 9. The high voltage MOS transistor according to claim 1wherein the source doping region and the drain doping region are bothformed in the first ion well.
 10. The high voltage MOS transistoraccording to claim 1 wherein a shallow trench isolation (STI) regionsurrounds the active area.
 11. The high voltage MOS transistor accordingto claim 1 wherein the gate comprises a sidewall spacer.
 12. Ahigh-voltage MOS transistor, comprising: a gate overlying an active areaof a semiconductor substrate; a drain structure of a first conductivitytype at one side of the gate, wherein the drain structure comprises afirst heavily doping region spaced apart from a second heavily dopingregion that is proximate to the gate, a first lightly doped regioninterposed between the first and second heavily doping regions, and asecond lightly doped region between the gate and the second heavilydoping region; a source doping region of the first conductivity type ina first ion well of a second conductivity type at the other side of thegate; and a third lightly doped region of the first conductivity typebetween the gate and the source doping region.
 13. The high voltage MOStransistor according to claim 12, wherein the semiconductor substrate isof the second conductivity type, the high voltage MOS transistor furthercomprises a second ion well of the first conductivity type in thesemiconductor substrate for bulk isolation, wherein the first ion wellis above the second ion well.
 14. The high voltage MOS transistoraccording to claim 12 wherein the drain structure is not formed in thefirst ion well.
 15. The high voltage MOS transistor according to claim12 wherein the drain structure, the source doping region and the thirdlightly doped region are formed in the first ion well.
 16. The highvoltage MOS transistor according to claim 12 wherein the gate comprisestwo portions: a first portion and a second portion, and wherein thefirst portion of the gate has a first concentration of dopants, thesecond portion, which is proximate to the drain doping region, has asecond concentration of dopants.
 17. The high voltage MOS transistoraccording to claim 16 wherein the second concentration is lower than thefirst concentration.
 18. The high voltage MOS transistor according toclaim 12 wherein a shallow trench isolation (STI) region surrounds theactive area.
 19. The high voltage MOS transistor according to claim 12wherein the gate comprises a sidewall spacer.